1. Field of the Invention
The following invention relates to a method and apparatus for realizing sample and hold type fractional-N synthesizers for use in any system that requires a fractional resolution of a reference frequency, and in particular, to a PLL-based frequency synthesizer for use in communication systems whether wireless or wired.
2. Background of the Related Art
Frequency synthesizers used in modern wireless communication systems typically utilize a Phase Locked Loop (PLL). PLLs usually include a voltage controlled oscillator (VCO), phase detector (PD) and loop filter (LF). To integrate a PLL on a single integrated circuit, a large LF capacitor, which is used to stabilize the PLL, occupies most of the chip area of the circuit because the capacitance needed in the loop filter (LF) is often on the order of several micro-farads. As recent wireless systems are attempting to integrate the overall receiver and transmitter (including the PLL) on a single chip the required capacitance of the LF capacitor is a significant problem.
One related art approach to reduce the LF capacitance is to use a sample-and-hold circuit as a phase detector or comparator. The capacitor in the sample-and-hold circuit has a much smaller capacitance than that in a typical loop filter. The other advantage of a sample-and-hold phase detector is that the output contains no high frequency harmonics of the input frequency. If the phase is constant, the output voltage is also constant. Hence, the sample-and-hold PD is applicable to a frequency synthesizer.
U.S. Pat. No. 6,137,372 discloses a sample-and-hold type PLL frequency synthesizer that does not need a large LF capacitor. The U.S. Pat. No. 6,137,372 sample-and-hold PLL frequency synthesizer uses an integer-N architecture to generate output frequencies that are integer multiples of a reference frequency. However, in the integer-N architecture, the loop bandwidth is limited because the input reference frequency must be equal to the channel spacing. Hence, the attenuation of the close-in phase noise is also limited, because the phase noise of the oscillator is reduced only within the bandwidth of the loop. Another disadvantage of the integer-N architecture is a slow lock time since the lock time of the PLL is also dependent on the loop bandwidth.
To increase the loop bandwidth, fractional-N architectures have been used for frequency synthesizers. In fractional-N synthesizers, the output frequency FOUT can vary by a fraction of the input frequency. Therefore, the input reference frequency can be much greater than the channel spacing and the loop bandwidth is much higher than that of the integer-N synthesizer. In fractional-N synthesizers, however, the phase relationship between the input reference clock and the divided VCO output varies in accordance with the accumulator state. In contrast, the phase relationship is constant in an integer-N synthesizer. Hence, in a conventional fractional-N synthesizer, the sample-and-hold method cannot be realized because the control voltage of the VCO varies in each phase comparison. Moreover, the phase noise and spurious tones that result are above the desired limit and not tolerable in most wireless communication systems.
FIG. 1 illustrates a related art frequency synthesizer using a sample-and-hold circuit. As shown in FIG. 1, the reference frequency divider 104 divides an input reference frequency 102 and produces a divided reference signal 106. The phase detector (PD) 110, receives the divided reference signal 106 and an output 108 of an integer divider 128 and generates an output signal 112 responsive to a comparison thereof. A sample and hold circuit 114 receives the output 112 of the PD 110. A voltage controlled oscillator 118 receives an output 116 of the sample and hold circuit 114. An output 120 of the voltage controlled oscillator 118 is an output signal FOUT of the frequency synthesizer circuit and is also input to the integer divider 128.
In operation, the VCO output signal 120 is divided by N in the integer divider 128 and then compared with the divided reference frequency 106 from the reference divider 104. A phase detector (PD) and the sample-and-hold circuit 130 generates a control signal that is dependent on a detected phase difference. The control signal is applied to the voltage controlled oscillator (VCO), which generates the output frequency FOUT.
FIG. 2 is an illustration of the related art phase detector and the sample-and-hold circuit 130. As shown in FIG. 2, a charge pump 206 receives an output 204 of a phase detector 202. An output 214 of the charge pump 206 is received by the sample and hold circuit 114 at an input connected to a first node n1. In the sample and hold circuit 114, a reference voltage Vref 210 is connected to the first node n1 through a first switch 212. A sample capacitor 220 is connected between a ground reference voltage 222 and the first node n1. A second switch 224 is connected between the first node n1 and a second node n2 that is connected to an output terminal 234. A hold capacitor 230 is connected between the ground reference voltage and the second node n2. The capacitance of the sample capacitor 220 and the hold capacitor 230 is much less than that of the typical loop filter. Before phase comparison occurs in the phase detector 202, the switch SW1 is closed and the sample capacitor is charged to the reference voltage Vref. The charge pump 206 following the phase detector 202 increases or decreases the voltage of the sample capacitor 220 from the reference voltage Vref according to the detected phase difference in the phase comparison. When the phase comparison is complete, the charge in the sample capacitor 220 is transferred to the hold capacitor 230 via the second switch SW2.
FIG. 3 is a timing diagram of the lock state in a related art sample-and-hold type integer-N frequency synthesizer. As shown in FIG. 3, a relationship between the reference frequency signal 302 and the divider output 304 (i.e., divided VCO output) exists and is a constant phase difference T when the phase is aligned in the typical loop filter type PLL. Hence, the sample-and-hold type PLL is not suitable for application as clock or data recovery where the phase must be aligned between the input reference signal and the VCO output. The phase detector output 306 and voltage of the sample capacitor 308 are also shown in FIG. 3. In the integer-N frequency synthesizer, however, the phase alignment is not a requirement, and the sample-and-hold type PLL is applicable as long as the phase noise characteristic is satisfied. As shown in FIG. 3, it is assumed that the phase of the reference frequency signal 302 leads that of the divider output 304 by the time T, and the phase detector generates an UP (HIGH) signal at every phase comparison to increase the voltage of the sample capacitor (Vsample) at a fixed rate from the reference voltage (Vref). Hence, the voltage of the hold capacitor (Vhold) and the output frequency of the voltage controlled oscillator are kept constant.
As described previously, however, an integer-N frequency synthesizer has a narrower loop bandwidth than a fractional-N frequency synthesizer. To increase the loop bandwidth above the channel spacing, the fractional-N synthesizer includes a variable modulus programmable divider, which is controlled by an accumulator. The accumulator changes the division ratio of the variable modulus programmable divider regularly to generate the desired fractional division ratio. Accordingly, the control voltage of the VCO in the fractional-N frequency synthesizer is not constant, but the time-averaged value of the control voltage is meaningful. Thus, the related art fractional-N architecture cannot adopt the sample-and-hold circuit to replace the loop filter.
FIG. 4 is a timing diagram that illustrates problems and disadvantages of a sample-and-hold circuit in the related art fractional-N synthesizer. As shown in FIG. 4, the reference frequency 402 and the divider output 404 do not have a constant aligned phase difference as shown in the phase detector output 306 of FIG. 3. The phase detector output 406, the sample-and-hold circuit output voltage 408 and the state of the fractional accumulator 410 are also shown. In FIG. 4, the fractional ratio is assumed to be xe2x85x9c (K=3 N=8) where N is the division factor. The state of the fractional accumulator varies according to the fractional ratio. Therefore, the phase of the divider output 404 with respect to the reference frequency signal 402 and the width of the UP pulse of the phase detector 406 also vary. The amount of voltage change of the sample capacitor (Vsample) is not fixed and the voltage of the hold capacitor (Vhold) shows fractional ripple which degrades the spectral purity of the synthesized frequency.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a phase locked loop-based fractional-N synthesizer.
Another object of the present invention is to provide a fractional compensation circuit and method that incorporates a sample-and-hold circuit in a loop filter.
Another object of the present invention is to incorporate fractional spur compensation circuitry that dynamically compensates spurious signals.
Another object of the present invention is to provide a phase locked loop-based fractional-N synthesizer and method that uses a plurality of phase detectors to dynamically cancel spurious signals and a sample-and-hold circuit.
Another object of the present invention is to provide a phase locked loop-based fractional-N synthesizer and method that reduces fractional spurs and charge pump ripple whenever the charge pump operates.
Another object of the present invention is to provide a fractional compensation circuit that uses a charge pump stage composed of N charge pumps coupled to a sample-and-hold circuit in a loop filter so that a number of the N charge pumps that operate during a phase comparison is determined by a fractional accumulator stage.
An advantage of a fractional-N architecture and method according to the present invention is that a reference frequency is not restricted by the channel spacing and loop bandwidths can be increased.
Another advantage of a fractional-N architecture and method according to the present invention is that circuit size is reduced.
Another advantage of a fractional-N architecture and method according to the present invention is that the spurious signal cancellation can occur dynamically.
Another advantage of a fractional-N architecture and method according to the present invention is that it avoids the need for a large loop filter capacitor.
Another advantage of a fractional-N architecture and method according to the present invention is that a sample-and-hold circuit can be implemented in the PLL to provide a stable control voltage.
To achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a phase locked loop that includes a first phase detector that receives an input signal and a first divided signal to output a first comparison signal, a second phase detector that receives the input signal and a second divided signal to output a second comparison signal, a sample-and-hold circuit that receives the first and second comparison signals and generates an output signal responsive to the comparison signals, a voltage-controlled oscillator that receives the output signal from the sample-and-hold circuit and generates a prescribed frequency signal, and a modulus divider that receives the prescribed frequency signal and generates the first and second divided signals having a prescribed phase relationship.
To further achieve the above objects in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a fractional-N frequency synthesizer for a mobile terminal including a phase detector circuit that includes a first phase detector having a first input port coupled to receive a reference signal, a second input port, a third input port and an output port, and a second phase detector having a first input port coupled to receive the reference signal, a second input port, a third input port and an output port, a sample-and-hold circuit having a first input port coupled to the output ports of the first and second phase detectors and an output port, a voltage-controlled oscillator having an input port coupled to the output port of the sample-and-hold circuit and transmitting a prescribed frequency signal at an output port, a programmable modulus divider having a first output port coupled to the second input port of the first phase detector to transmit a first divided signal, a second output port coupled to the second input port of the second phase detector to transmit a second divided signal, a first input port coupled to the output port of the voltage-controlled oscillator and a second input port, and an accumulator having a first output port coupled to the second input port of the programmable modulus divider and a second output port coupled to the third input ports of the phase detectors.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.